Fpga Based Implementation of Double Precision Floating Point Adder/subtractor Using Verilog
نویسنده
چکیده
Floating Point operations is widely used in many areas, especially in signal processing. The greater dynamic range and lack of need to scale the numbers makes development of algorithms much easier. However, implementing arithmetic operations for floating point numbers in hardware is very difficult. The IEEE floating point standard defines both single precision (32-bit) and double precision (64-bit) formats. In this paper a double precision floating point adder/subtractor is implemented using Verilog. The code is dumped into vertex-5 FPGA.
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An Implementation of Double precision Floating point Adder & Subtractor Using Verilog
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